By Okwan Kwon, Fahed Jubair, Seung-Jai Min (auth.), Sanjay Rajopadhye, Michelle Mills Strout (eds.)

This booklet constitutes the completely refereed post-conference lawsuits of the twenty fourth foreign Workshop on Languages and Compilers for Parallel Computing, LCPC 2011, held in castle Collins, CO, united states, in September 2011. the nineteen revised complete papers awarded and 19 poster papers have been rigorously reviewed and chosen from fifty two submissions. The scope of the workshop spans the theoretical and useful features of parallel and high-performance computing, and goals parallel structures together with concurrent, multithreaded, multicore, accelerator, multiprocessor, and cluster systems.

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Additional resources for Languages and Compilers for Parallel Computing: 24th International Workshop, LCPC 2011, Fort Collins, CO, USA, September 8-10, 2011. Revised Selected Papers

Example text

However, when two parallel inspectors try to register in a book-keeping data structure that a single address is being touched, this will – at least conceptually – require slow synchronization or critical sections to guard the tracking data structure. Thus, it is essential to avoid such synchronization wherever possible. This is even more difficult on modern multicores as their memory systems are typically not sequentially consistent and cores might see changes at different times. And even with the synchronization demands solved, the individual effort for registering every single address must be kept tiny and without branches to keep the processor pipelines busy.

4 Performance of Simultaneous Execution of Multiple High-Processing-Load Applications (MPEG2 decoder) Figure 9 shows power consumption of MPEG2 decoder multiple executions. horizontal axis indicates sum of processor PEs used by 352x128 resolution MPEG2 decoder and 352x240 resolution MPEG2 decoder. Vertical axis indicates power consumption of entire chip. When different resolution MPEG2 decoders are executed multiple, timing of FV control are differ. This is because execution time of each decode stage are different.

The OSCAR compiler has realized an automatic power control scheme using DVFS and Power Gating for each core on a multicore with automatic parallelization of an application program under the constraints of the minimum time execution or the satisfaction of real-time deadline, or realtime execution. However, no paper has evaluated power consumed by multiple application programs parallelized and power controlled by a compiler. 0V three levels of voltage states and power gating for individual cores in 5 micro seconds power shut-down and 30 micro seconds power recovery when multiple media applications parallelized and power-controlled by OSCAR comoiler are executed simultaneously.

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Languages and Compilers for Parallel Computing: 24th by Okwan Kwon, Fahed Jubair, Seung-Jai Min (auth.), Sanjay
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